Dynamic random access memory (DRAM) cells are employed in the semiconductor industry to provide a high density memory unit. An array of DRAM cells may be employed in a stand-alone memory chip, i.e., a dedicated DRAM chip. Alternately, an array of DRAM cells may be incorporated as embedded memory elements into an integrated semiconductor chip, which may include a processor unit.
Typical DRAM cells employ many unique processing steps, thereby significantly increasing processing time and processing cost for a semiconductor chip including such DRAM cells. In general, the less processing complexity and processing time a DRAM cell structure requires, the better the manufacturability of a semiconductor chip including such DRAM cells.
A challenge facing scaling of conventional DRAM cell structures is short channel effects. As the length of an access transistor controlling the current flow in a DRAM cell decreases with scaling, the short channel effect also increases, thereby increasing the off-current and/or decreasing the on-current. Increase in the off-current adversely impacts the retention time of a DRAM cell. Decrease in the on-current adversely impacts the access time of the DRAM cell. Reduction of the short channel effects is therefore a key consideration in the design of a DRAM cell.